The present invention relates to a semiconductor device tester generating various test patterns.
FIG. 1 shows a conventional semiconductor device tester, which comprises a random pattern data generator (hereinafter referred to as RPG) 1 for generating and storing test patterns which varies randomly, an algorithmic pattern data generator (hereinafter referred to as ALPG) 2 for generating test pattern data by arithmetic and logic operations, e.g., by continuous counting, a serial pattern data generator (hereinafter referred to as SPG) 3 for generating and storing serial test pattern data, a first switching unit (hereinafter referred to as AMUX) 4 for selecting, in accordance with a switch control signal A, the test pattern data from the ALPG 2 or the test pattern data from the SPG 3, a second switching unit (hereinafter referred to as BMUX) 5 for selecting, in accordance with the switch control signal B, the test pattern data from the RPG 1 or the test pattern data from the AMUX 4. The outputs of the BMUX 5 are connected to channels P which are connected to the terminals or pins of a semiconductor device under test (hereinafter referred to as DUT), not shown, and through which the test pattern data are supplied to the pins of the DUT.
An example of test pattern data to be applied to the pins of the DUT is shown in FIG. 2, in which the numbers x in the horizontal direction are the respective numbers of the pins of the DUT. The largest number X is 256, for example. The numbers y in the vertical direction are the respective "cycle numbers" representing progress of time, and normally correspond to the respective numbers of the test pattern data generated by the RPG 1. The largest number Y is 1048576 (=1024.times.1024=1 Mbits), for example. The number X of pins of the DUT corresponds to the number of the channels P and the pins are respectively connected to the channels. Therefore the references P1 to PN are sometimes used for the pins as well as the channels.
The combinations of 0,1 of the first pin P1 (x=1) of the DUT appear randomly with time. This means that the data (random test pattern data) on the first channel P1 are derived from the RPG 1. In regard to the second and third pins P2 and P3 (x=2 and x=3), 8 cycles of 0's and 1's appear in alternation. These data (serial test data pattern) are derived from the SPG3. The data on the fourth to seventh pins P4 to P7 (x=4 to x=7) of the DUT are identical to successive outputs of a 4-bit counter counting the number of the cycles (y), that is the value of the data is successively incremented by 1. At each 16th cycle (e.g., at y=15), all the bits on the pins P4 to P7 are 1 and the value of the data returns to "0000" at the immediately succeeding cycle. Thus in the example of FIG. 2, the data on the pins P4 to P7 are derived from the ALPG 3. It takes 16 cycles for all possible permutations of the four bits for the four pins P4 to P7 to appear in turn.
Another example of test pattern data to be applied to the pins of the DUT is shown in FIG. 3, in which data on the first to third pins P1 to P3 are identical to those of FIG. 2. But the data on the fourth pin P4 are different. As will been seen, the data on the fourth pin P4 can be considered as an output of a counter if combinations each consisting of four successive bits are taken as units, and the figures of the larger cycle numbers are seen as the lower bits. For instance, the 0th to 3rd cycle form "0000", while the 4th to 7th cycles form "0001", and the 8th to 11th cycles form "0010", and so on. For all possible permutations of the four successive cycles to appear in turn, it takes 64 cycles. In other words, a sequence of such data takes 64 cycles to complete. To provide this sequence of data, the RPG1 or the SPG3 must store a very long series of data. This requires a very large amount of work during preparation of the test pattern.